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512 Kbit (64K x8) Page-Write EEPROM
SST29EE512
SST29EE512512Kb (x8) Page-Write, Small-Sector flash memories
Data Sheet
FEATURES:
* Single Voltage Read and Write Operations - 4.5-5.5V for SST29EE512 * Superior Reliability - Endurance: 100,000 Cycles (typical) - Greater than 100 years Data Retention * Low Power Consumption - Active Current: 20 mA (typical) - Standby Current: 10 A (typical) * Fast Page-Write Operation - 128 Bytes per Page, 512 Pages - Page-Write Cycle: 5 ms (typical) - Complete Memory Rewrite: 2.5 sec (typical) - Effective Byte-Write Cycle Time: 39 s (typical) * Fast Read Access Time - 4.5-5.5V operation: 70 ns * Latched Address and Data * Automatic Write Timing - Internal VPP Generation * End of Write Detection - Toggle Bit - Data# Polling * Hardware and Software Data Protection * Product Identification can be accessed via Software Operation * TTL I/O Compatibility * JEDEC Standard - Flash EEPROM Pinouts and command sets * Packages Available - 32-lead PLCC - 32-lead TSOP (8mm x 20mm) - 32-pin PDIP * All non-Pb (lead-free) devices are RoHS compliant
PRODUCT DESCRIPTION
The SST29EE512 is a 64K x8 CMOS, Page-Write EEPROM manufactured with SST's proprietary, high-performance CMOS SuperFlash technology. The split-gate cell design and thick-oxide tunneling injector attain better reliability and manufacturability compared with alternate approaches. The SST29EE512 writes with a single power supply. Internal Erase/Program is transparent to the user. The SST29EE512 conforms to JEDEC standard pin assignments for byte-wide memories. Featuring high performance Page-Write, the SST29EE512 provides a typical Byte-Write time of 39 sec. The entire memory, i.e., 64 KByte, can be written page-by-page in as little as 2.5 seconds, when using interface features such as Toggle Bit or Data# Polling to indicate the completion of a Write cycle. To protect against inadvertent write, the SST29EE512 have on-chip hardware and Software Data Protection schemes. Designed, manufactured, and tested for a wide spectrum of applications, the SST29EE512 is offered with a guaranteed Page-Write endurance of 10,000 cycles. Data retention is rated at greater than 100 years. The SST29EE512 is suited for applications that require convenient and economical updating of program, configuration, or data memory. For all system applications, the SST29EE512 significantly improves performance and reliability, while lowering power consumption. The SST29EE512 improves flexibility while lowering the cost for program, data, and configuration storage applications. To meet high density, surface mount requirements, the SST29EE512 is offered in 32-lead PLCC and 32-lead TSOP packages. A 600-mil, 32-pin PDIP package is also available. See Figures 1, 2, and 3 for pin assignments.
Device Operation
The SST Page-Write EEPROM offers in-circuit electrical write capability. The SST29EE512 does not require separate Erase and Program operations. The internally timed Write cycle executes both erase and program transparently to the user. The SST29EE512 has industry standard optional Software Data Protection, which SST recommends always to be enabled. The SST29EE512 is compatible with industry standard EEPROM pinouts and functionality.
(c)2005 Silicon Storage Technology, Inc. S71060-09-000 9/05 1
The SST logo and SuperFlash are registered trademarks of Silicon Storage Technology, Inc. SSF is a trademark of Silicon Storage Technology, Inc. These specifications are subject to change without notice.
512 Kbit Page-Write EEPROM SST29EE512
Data Sheet
Read
The Read operations of the SST29EE512 is controlled by CE# and OE#, both have to be low for the system to obtain data from the outputs. CE# is used for device selection. When CE# is high, the chip is deselected and only standby power is consumed. OE# is the output control and is used to gate data from the output pins. The data bus is in high impedance state when either CE# or OE# is high. Refer to the Read cycle timing diagram for further details (Figure 4).
writing to the selected page and will leave the SST29EE512 protected at the end of the Page-Write. The page-load cycle consists of loading 1 to 128 Bytes of data into the page buffer. The internal Write cycle consists of the TBLCO time-out and the write timer operation. During the Write operation, the only valid reads are Data# Polling and Toggle Bit. The Page-Write operation allows the loading of up to 128 Bytes of data into the page buffer of the SST29EE512 before the initiation of the internal Write cycle. During the internal Write cycle, all the data in the page buffer is written simultaneously into the memory array. Hence, the PageWrite feature of SST29EE512 allows the entire memory to be written in as little as 2.5 seconds. During the internal Write cycle, the host is free to perform additional tasks, such as to fetch data from other locations in the system to set up the write to the next page. In each Page-Write operation, all the bytes that are loaded into the page buffer must have the same page address, i.e. A7 through A16. Any byte not loaded with user data will be written to FFH. See Figures 5 and 6 for the Page-Write cycle timing diagrams. If after the completion of the three-byte SDP load sequence or the initial byte-load cycle, the host loads a second byte into the page buffer within a byte-load cycle time (TBLC) of 100 s, the SST29EE512 will stay in the pageload cycle. Additional bytes are then loaded consecutively. The page-load cycle will be terminated if no additional byte is loaded into the page buffer within 200 s (TBLCO) from the last byte-load cycle, i.e., no subsequent WE# or CE# high-to-low transition after the last rising edge of WE# or CE#. Data in the page buffer can be changed by a subsequent byte-load cycle. The page-load period can continue indefinitely, as long as the host continues to load the device within the byte-load cycle time of 100 s. The page to be loaded is determined by the page address of the last byte loaded.
Write
The Page-Write to the SST29EE512 should always use the JEDEC Standard Software Data Protection (SDP) three-byte command sequence. The SST29EE512 contains the optional JEDEC approved Software Data Protection scheme. SST recommends that SDP always be enabled, thus, the description of the Write operations will be given using the SDP enabled format. The three-byte SDP Enable and SDP Write commands are identical; therefore, any time a SDP Write command is issued, Software Data Protection is automatically assured. The first time the three-byte SDP command is given, the device becomes SDP enabled. Subsequent issuance of the same command bypasses the data protection for the page being written. At the end of the desired Page-Write, the entire device remains protected. For additional descriptions, please see the application notes The Proper Use of JEDEC Standard Software Data Protection and Protecting Against Unintentional Writes When Using Single Power Supply Flash Memories. The Write operation consists of three steps. Step 1 is the three-byte load sequence for Software Data Protection. Step 2 is the byte-load cycle to a page buffer of the SST29EE512. Steps 1 and 2 use the same timing for both operations. Step 3 is an internally controlled Write cycle for writing the data loaded in the page buffer into the memory array for nonvolatile storage. During both the SDP threebyte load sequence and the byte-load cycle, the addresses are latched by the falling edge of either CE# or WE#, whichever occurs last. The data is latched by the rising edge of either CE# or WE#, whichever occurs first. The internal Write cycle is initiated by the TBLCO timer after the rising edge of WE# or CE#, whichever occurs first. The Write cycle, once initiated, will continue to completion, typically within 5 ms. See Figures 5 and 6 for WE# and CE# controlled Page-Write cycle timing diagrams and Figures 15 and 17 for flowcharts. The Write operation has three functional cycles: the Software Data Protection load sequence, the page-load cycle, and the internal Write cycle. The Software Data Protection consists of a specific three-byte load sequence that allows
(c)2005 Silicon Storage Technology, Inc.
Software Chip-Erase
The SST29EE512 provides a Chip-Erase operation, which allows the user to simultaneously clear the entire memory array to the "1" state. This is useful when the entire device must be quickly erased. The Software Chip-Erase operation is initiated by using a specific six-byte load sequence. After the load sequence, the device enters into an internally timed cycle similar to the Write cycle. During the Erase operation, the only valid read is Toggle Bit. See Table 4 for the load sequence, Figure 10 for timing diagram, and Figure 19 for the flowchart.
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Data Sheet
Write Operation Status Detection
The SST29EE512 provides two software means to detect the completion of a Write cycle, in order to optimize the system Write cycle time. The software detection includes two status bits: Data# Polling (DQ7) and Toggle Bit (DQ6). The end of write detection mode is enabled after the rising WE# or CE# whichever occurs first, which initiates the internal Write cycle. The actual completion of the nonvolatile write is asynchronous with the system; therefore, either a Data# Polling or Toggle Bit read may be simultaneous with the completion of the Write cycle. If this occurs, the system may possibly get an erroneous result, i.e., valid data may appear to conflict with either DQ7 or DQ6. In order to prevent spurious rejection, if an erroneous result occurs, the software routine should include a loop to read the accessed location an additional two (2) times. If both reads are valid, then the device has completed the Write cycle, otherwise the rejection is valid.
Hardware Data Protection
Noise/Glitch Protection: A WE# or CE# pulse of less than 5 ns will not initiate a Write cycle. VDD Power Up/Down Detection: The Write operation is inhibited when VDD is less than 2.5V. Write Inhibit Mode: Forcing OE# low, CE# high, or WE# high will inhibit the Write operation. This prevents inadvertent writes during power-up or power-down.
Software Data Protection (SDP)
The SST29EE512 provides the JEDEC approved optional Software Data Protection scheme for all data alteration operations, i.e., Write and Chip-Erase. With this scheme, any Write operation requires the inclusion of a series of three byte-load operations to precede the data loading operation. The three-byte load sequence is used to initiate the Write cycle, providing optimal protection from inadvertent Write operations, e.g., during the system power-up or power-down. The SST29EE512 is shipped with the Software Data Protection disabled. The software protection scheme can be enabled by applying a three-byte sequence to the device, during a page-load cycle (Figures 5 and 6). The device will then be automatically set into the data protect mode. Any subsequent Write operation will require the preceding three-byte sequence. See Table 4 for the specific software command codes and Figures 5 and 6 for the timing diagrams. To set the device into the unprotected mode, a six-byte sequence is required. See Table 4 for the specific codes and Figure 9 for the timing diagram. If a Write is attempted while SDP is enabled the device will be in a non-accessible state for ~ 300 s. SST recommends Software Data Protection always be enabled. See Figure 17 for flowcharts. The SST29EE512 Software Data Protection is a global command, protecting (or unprotecting) all pages in the entire memory array once enabled (or disabled). Therefore using SDP for a single Page-Write will enable SDP for the entire array. Single pages by themselves cannot be SDP enabled or disabled, although the page addressed during the SDP write will be written. Single power supply reprogrammable nonvolatile memories may be unintentionally altered. SST strongly recommends that Software Data Protection (SDP) always be enabled. The SST29EE512 should be programmed using the SDP command sequence. SST recommends the SDP Disable Command Sequence not be issued to the device prior to writing.
Data# Polling (DQ7)
When the SST29EE512 is in the internal Write cycle, any attempt to read DQ7 of the last byte loaded during the byteload cycle will receive the complement of the true data. Once the Write cycle is completed, DQ7 will show true data. Note that even though DQ7 may have valid data immediately following the completion of an internal Write operation, the remaining data outputs may still be invalid: valid data on the entire data bus will appear in subsequent successive Read cycles after an interval of 1 s. See Figure 7 for Data# Polling timing diagram and Figure 16 for a flowchart.
Toggle Bit (DQ6)
During the internal Write cycle, any consecutive attempts to read DQ6 will produce alternating `0's and `1's, i.e., toggling between 0 and 1. When the Write cycle is completed, the toggling will stop. The device is then ready for the next operation. See Figure 8 for Toggle Bit timing diagram and Figure 16 for a flowchart. The initial read of the Toggle Bit will typically be a "1".
Data Protection
The SST29EE512 provide both hardware and software features to protect nonvolatile data from inadvertent writes.
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512 Kbit Page-Write EEPROM SST29EE512
Data Sheet Please refer to the following Application Notes for more information on using SDP: * * Protecting Against Unintentional Writes When Using Single Power Supply Flash Memories The Proper Use of JEDEC Standard Software Data Protection TABLE 1: PRODUCT IDENTIFICATION
Address Manufacturer's ID Device ID SST29EE512 0001H 5DH
T1.3 1060
Data BFH
0000H
Product Identification
The Product Identification mode identifies the device as the SST29EE512 and manufacturer as SST. This mode is accessed via software. For details, see Table 4, Figure 11 for the software ID entry, and Read timing diagram and Figure 18 for the ID entry command sequence flowchart.
Product Identification Mode Exit
In order to return to the standard Read mode, the Software Product Identification mode must be exited. Exiting is accomplished by issuing the Software ID Exit (reset) operation, which returns the device to the Read operation. The Reset operation may also be used to reset the device to the Read mode after an inadvertent transient condition that apparently causes the device to behave abnormally, e.g., not read correctly. See Table 4 for software command codes, Figure 12 for timing waveform, and Figure 18 for a flowchart.
FUNCTIONAL BLOCK DIAGRAM
X-Decoder
SuperFlash Memory
A15 - A0
Address Buffer & Latches Y-Decoder and Page Latches
CE# OE# WE#
Control Logic
I/O Buffers and Data Latches DQ7 - DQ0
1060 B1.1
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Data Sheet
WE#
VDD
A12
A15
NC
NC
A7 A6 A5 A4 A3 A2 A1 A0 DQ0
5 6 7 8 9 10 11 12 13
4
3
2
1
32 31 30 29 28 27 26 25 24 23 22
NC
A14 A13 A8 A9 A11 OE# A10 CE# DQ7
32-lead PLCC Top View
21 14 15 16 17 18 19 20 DQ1 DQ2 VSS DQ3 DQ4 DQ5 DQ6
1060 32-plcc NH P1.0
FIGURE 1: PIN ASSIGNMENTS FOR 32-LEAD PLCC
A11 A9 A8 A13 A14 NC WE# VDD NC NC A15 A12 A7 A6 A5 A4
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
Standard Pinout Top View Die Up
32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17
OE# A10 CE# DQ7 DQ6 DQ5 DQ4 DQ3 VSS DQ2 DQ1 DQ0 A0 A1 A2 A3
1060 32-tsop EH P2.0
FIGURE 2: PIN ASSIGNMENTS FOR 32-LEAD TSOP
NC NC A15 A12 A7 A6 A5 A4 A3 A2 A1 A0 DQ0 DQ1 DQ2 VSS
1 2 3 4 5 32-pin 6 PDIP 7 8 Top View 9 10 11 12 13 14 15 16
32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17
VDD WE# NC A14 A13 A8 A9 A11 OE# A10 CE# DQ7 DQ6 DQ5 DQ4 DQ3
1060 32-pdip PH P3.0
FIGURE 3: PIN ASSIGNMENTS FOR 32-PIN PDIP
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512 Kbit Page-Write EEPROM SST29EE512
Data Sheet TABLE 2: PIN DESCRIPTION
Symbol A15-A7 A6-A0 Pin Name Row Address Inputs Column Address Inputs Data Input/output Functions To provide memory addresses. Row addresses define a page for a Write cycle. Column Addresses are toggled to load page data To output data during Read cycles and receive input data during Write cycles. Data is internally latched during a Write cycle. The outputs are in tri-state when OE# or CE# is high. To activate the device when CE# is low. To gate the data output buffers. To control the Write operations. To provide: 5.0V supply (4.5-5.5V) for SST29EE512
DQ7-DQ0
CE# OE# WE# VDD VSS NC
Chip Enable Output Enable Write Enable Power Supply Ground No Connection
Unconnected pins.
T2.3 1060
TABLE 3: OPERATION MODES SELECTION
Mode Read Page-Write Standby Write Inhibit Software Chip-Erase Product Identification Software Mode SDP Enable Mode SDP Disable Mode VIL VIL VIL VIH VIH VIH VIL VIL VIL Manufacturer's ID (BFH) Device ID2 See Table 4 See Table 4 See Table 4
T3.4 1060
CE# VIL VIL VIH X X VIL
OE# VIL VIH X1 VIL X VIH
WE# VIH VIL X X VIH VIL
DQ DOUT DIN High Z High Z/ DOUT High Z/ DOUT DIN
Address AIN AIN X X X AIN, See Table 4
1. X can be VIL or VIH, but no other value. 2. Device ID = 5DH for SST29EE512
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Data Sheet TABLE 4: SOFTWARE COMMAND SEQUENCE
Command Sequence Software Data Protect Enable & Page-Write Software ID Entry4,5 Software ID Exit Alternate Software ID Entry6 1st Bus Write Cycle Addr1 5555H Data AAH 2nd Bus Write Cycle Addr1 2AAAH Data 55H 3rd Bus Write Cycle Addr1 5555H Data A0H 4th Bus Write Cycle Addr1 Addr2 Data Data 5th Bus Write Cycle Addr1 Data 6th Bus Write Cycle Addr1 Data
Software Chip-Erase3 5555H 5555H 5555H 5555H
AAH AAH AAH AAH
2AAAH 2AAAH 2AAAH 2AAAH
55H 55H 55H 55H
5555H 5555H 5555H 5555H
80H 90H F0H 80H
5555H
AAH
2AAAH
55H
5555H
10H
5555H
AAH
2AAAH
55H
5555H
60H
T4.4 1060
1. Address format A14-A0 (Hex), Address A15 can be VIL or VIH, but no other value." 2. Page-Write consists of loading up to 128 Bytes (A6-A0) 3. The software Chip-Erase function is not supported by the industrial temperature part. Please contact SST if you require this function for an industrial temperature part. 4. The device does not remain in Software Product ID mode if powered down. 5. With A14-A1 = 0; SST Manufacturer's ID = BFH, is read with A0 = 0, SST29EE512 Device ID = 5DH, is read with A0 = 1 6. Alternate six-byte Software Product ID Command Code Note: This product supports both the JEDEC standard three-byte command code sequence and SST's original six-byte command code sequence. For new designs, SST recommends that the three-byte command code sequence be used.
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Data Sheet Absolute Maximum Stress Ratings (Applied conditions greater than those listed under "Absolute Maximum Stress Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these conditions or conditions greater than those defined in the operational sections of this data sheet is not implied. Exposure to absolute maximum stress rating conditions may affect device reliability.) Temperature Under Bias . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55C to +125C Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65C to +150C D. C. Voltage on Any Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to VDD+0.5V Transient Voltage (<20 ns) on Any Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -2.0V to VDD+2.0V Voltage on A9 Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 14.0V Package Power Dissipation Capability (TA = 25C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.0W Through Hole Lead Soldering Temperature (10 Seconds) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300C Surface Mount Solder Reflow Temperature1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260C for 10 seconds Output Short Circuit Current2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 mA
1. Excluding certain with-Pb 32-PLCC units, all packages are 260C capable in both non-Pb and with-Pb solder versions. Certain with-Pb 32-PLCC package types are capable of 240C for 10 seconds; please consult the factory for the latest information. 2. Outputs shorted for no more than one second. No more than one output shorted at a time.
OPERATING RANGE FOR SST29EE512
Range Commercial Industrial Ambient Temp 0C to +70C -40C to +85C VDD 4.5-5.5V 4.5-5.5V
AC CONDITIONS OF TEST
Input Rise/Fall Time . . . . . . . . . . . . . . 10 ns Output Load . . . . . . . . . . . . . . . . . . . . . 1 TTL Gate and CL = 100 pF See Figures 13 and 14
TABLE 5: DC OPERATING CHARACTERISTICS VDD = 4.5-5.5V FOR SST29EE512
Limits Symbol IDD Parameter Power Supply Current Read Program and Erase ISB1 ISB2 ILI ILO VIL VIH VOL VOH Standby VDD Current (TTL input) Standby VDD Current (CMOS input) Input Leakage Current Output Leakage Current Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage 2.4 2.0 0.4 30 50 3 50 1 10 0.8 mA mA mA A A A V V V V Min Max Units Test Conditions Address input=VILT/VIHT, at f=1/TRC Min, VDD=VDD Max CE#=OE#=VIL, WE#=VIH, all I/Os open CE#=WE#=VIL, OE#=VIH, VDD=VDD Max CE#=OE#=WE#=VIH, VDD=VDD Max CE#=OE#=WE#=VDD -0.3V, VDD=VDD Max VIN=GND to VDD, VDD=VDD Max VOUT=GND to VDD, VDD=VDD Max VDD=VDD Min VDD=VDD Max IOL=2.1 mA, VDD=VDD Min IOH=-400 A, VDD=VDD Min
T5.2 1060
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Data Sheet TABLE 6: RECOMMENDED SYSTEM POWER-UP TIMINGS
Symbol TPU-READ1 TPU-WRITE
1
Parameter Power-up to Read Operation Power-up to Write Operation
Minimum 100 5
Units s ms
T6.0 1060
1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.
TABLE 7: CAPACITANCE (TA = 25C, f=1 Mhz, other pins open)
Parameter CI/O1 CIN
1
Description I/O Pin Capacitance Input Capacitance
Test Condition VI/O = 0V VIN = 0V
Maximum 12 pF 6 pF
T7.0 1060
1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.
TABLE 8: RELIABILITY CHARACTERISTICS
Symbol NEND TDR1 ILTH1
1
Parameter Endurance Data Retention Latch Up
Minimum Specification 10,000 100 100
Units Cycles Years mA
Test Method JEDEC Standard A117 JEDEC Standard A103 JEDEC Standard 78
T8.5 1060
1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.
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Data Sheet
AC CHARACTERISTICS
TABLE 9: READ CYCLE TIMING PARAMETERS FOR SST29EE512
Symbol TRC TCE TAA TOE TCLZ1 TOLZ1 TCHZ TOH1
1
Parameter Read Cycle Time Chip Enable Access Time Address Access Time Output Enable Access Time CE# Low to Active Output OE# Low to Active Output CE# High to High-Z Output OE# High to High-Z Output Output Hold from Address Change
Min 70
Max 70 70 30
Units ns ns ns ns ns ns
0 0 20 20 0
ns ns ns
T9.3 1060
TOHZ1
1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.
TABLE 10: PAGE-WRITE CYCLE TIMING PARAMETERS
Symbol TWC TAS TAH TCS TCH TOES TOEH TCP TWP TDS TDH1 TBLC TIDA
1
Parameter Write Cycle (Erase and Program) Address Setup Time Address Hold Time WE# and CE# Setup Time WE# and CE# Hold Time OE# High Setup Time OE# High Hold Time CE# Pulse Width WE# Pulse Width Data Setup Time Data Hold Time Byte Load Cycle Time Byte Load Cycle Time Software ID Access and Exit Time Software Chip-Erase
Min 0 50 0 0 0 0 70 70 35 0 0.05 200
Max 10
Units ms ns ns ns ns ns ns ns ns ns ns
100 10 20
s s s ms
T10.6 1060
TBLCO1
1
TSCE
1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.
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Data Sheet
TRC ADDRESS A15-0 TCE CE# TOE OE# VIH WE# HIGH-Z DQ 7-0 TCLZ TOH DATA VALID TOLZ
TAA
TOHZ
TCHZ DATA VALID
1060 F04.0
FIGURE 4: READ CYCLE TIMING DIAGRAM
Three-Byte Sequence for Enabling SDP ADDRESS A15-0 5555 2AAA 5555
TAH TAS
TCS CE# TOES OE# TWP WE#
TCH
TOEH
TBLC
TBLCO
TDH DQ 7-0 AA SW0 55 SW1 A0 SW2 BYTE 0 DATA VALID TDS BYTE 1 BYTE 127
1060 F05.0
TWC
FIGURE 5: WE# CONTROLLED PAGE-WRITE CYCLE TIMING DIAGRAM
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Data Sheet
Three-Byte Sequence for Enabling SDP ADDRESS A15-0 5555 2AAA 5555
TAH TAS
TCP CE# TOES OE# TCS WE#
TBLC
TBLCO
TOEH
TCH
TDH DQ 7-0 AA SW0 55 SW1 A0 SW2 BYTE 0 DATA VALID TDS BYTE 1 BYTE 127
1060 F06.0
TWC
FIGURE 6: CE# CONTROLLED PAGE-WRITE CYCLE TIMING DIAGRAM
ADDRESS A15-0 TCE CE# TOEH OE# TOE WE# TOES
DQ 7
D
D# TWC + TBLCO
D#
D
1060 F07.0
FIGURE 7: DATA# POLLING TIMING DIAGRAM
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Data Sheet
ADDRESS A15-0 TCE CE# TOEH TOE OE# TOES
WE#
DQ6 TWC + TBLCO
TWO READ CYCLES WITH SAME OUTPUTS
1060 F08.0
FIGURE 8: TOGGLE BIT TIMING DIAGRAM
Six-Byte Sequence for Disabling Software Data Protection ADDRESS A14-0 5555 2AAA 5555 5555 2AAA 5555
TWC
DQ 7-0
AA
55
80
AA
55
20
CE#
OE# TWP WE# TBLC SW0 SW1 SW2 SW3 SW4 SW5
1060 F09.0
TBLCO
FIGURE 9: SOFTWARE DATA PROTECT DISABLE TIMING DIAGRAM
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Data Sheet
Six-Byte Code for Software Chip-Erase ADDRESS A14-0 5555 2AAA 5555 5555 2AAA 5555
TSCE
DQ 7-0
AA
55
80
AA
55
10
CE#
OE# TWP WE# TBLC SW0 SW1 SW2 SW3 SW4 SW5
1060 F10.0
TBLCO
FIGURE 10: SOFTWARE CHIP-ERASE TIMING DIAGRAM
Three-Byte Sequence for Software ID Entry ADDRESS A14-0 5555 2AAA 5555 0000 TAA DQ 7-0 AA 55 90 TIDA CE# BF 5D 0001
OE# TWP WE# TBLC SW0 SW1 SW2
1060 F11.0
FIGURE 11: SOFTWARE ID ENTRY AND READ
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Data Sheet
Three-Byte Sequence for Software ID Exit and Reset ADDRESS A14-0 5555 2AAA 5555
DQ 7-0
AA
55
F0 TIDA
CE#
OE# TWP WE# TBLC SW0 SW1 SW2
1060 F12.0
FIGURE 12: SOFTWARE ID EXIT AND RESET
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Data Sheet
VIHT VHT
INPUT REFERENCE POINTS
VHT
OUTPUT
VLT VILT
VLT
1060 F13.0
AC test inputs are driven at VIHT (2.4V) for a logic "1" and VILT (0.4 V) for a logic "0". Measurement reference points for inputs and outputs are VHT (2.0 V) and VLT (0.8 V). Input rise and fall times (10% 90%) are <10 ns.
Note: VHT - VHIGH Test VLT - VLOW Test VIHT - VINPUT HIGH Test VILT - VINPUT LOW Test
FIGURE 13: AC INPUT/OUTPUT REFERENCE WAVEFORMS
VDD TO TESTER RL HIGH
TO DUT CL RL LOW
1060 F14.0
FIGURE 14: A TEST LOAD EXAMPLE
(c)2005 Silicon Storage Technology, Inc.
S71060-09-000
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512 Kbit Page-Write EEPROM SST29EE512
Data Sheet
Start Software Data Protect Write Command
See Figure 17
Set Page Address
Set Byte Address = 0
Load Byte Data
Increment Byte Address By 1
No
Byte Address = 128? Yes Wait TBLCO
Wait for end of Write (TWC, Data# Polling bit or Toggle bit operation) Write Completed
FIGURE 15: WRITE ALGORITHM
1060 F15.0
(c)2005 Silicon Storage Technology, Inc.
S71060-09-000
9/05
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512 Kbit Page-Write EEPROM SST29EE512
Data Sheet
Internal Timer
Toggle Bit
Data# Polling
Page-Write Initiated
Page-Write Initiated
Page-Write Initiated
Wait TWC
Read a byte from page
Read DQ7 (Data for last byte loaded)
Write Completed
Read same byte
No
Is DQ7 = true data?
Yes No Write Completed
Does DQ6 match?
Yes Write Completed
1060 F16.0
FIGURE 16: WAIT OPTIONS
(c)2005 Silicon Storage Technology, Inc.
S71060-09-000
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512 Kbit Page-Write EEPROM SST29EE512
Data Sheet
Software Data Protect Enable Command Sequence Write data: AAH Address: 5555H
Software Data Protect Disable Command Sequence Write data: AAH Address: 5555H
Write data: 55H Address: 2AAAH
Write data: 55H Address: 2AAAH
Write data: A0H Address: 5555H
Write data: 80H Address: 5555H
Load 0 to 128 Bytes of page data
Optional Page Load Operation
Write data: AAH Address: 5555H
Wait TBLCO
Write data: 55H Address: 2AAAH
Wait TWC
Write data: 20H Address: 5555H
SDP Enabled
Wait TBLCO
Wait TWC
SDP Disabled
1060 F17.0
FIGURE 17: SOFTWARE DATA PROTECTION FLOWCHARTS
(c)2005 Silicon Storage Technology, Inc.
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512 Kbit Page-Write EEPROM SST29EE512
Data Sheet
Software Product ID Entry Command Sequence Write data: AAH Address: 5555H
Software Product ID Exit & Reset Command Sequence Write data: AAH Address: 5555H
Write data: 55H Address: 2AAAH
Write data: 55H Address: 2AAAH
Write data: 90H Address: 5555H
Write data: F0H Address: 5555H
Pause 10 s
Pause 10 s
Read Software ID
Return to normal operation
1060 F18.0
FIGURE 18: SOFTWARE PRODUCT COMMAND FLOWCHARTS
(c)2005 Silicon Storage Technology, Inc.
S71060-09-000
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512 Kbit Page-Write EEPROM SST29EE512
Data Sheet
Software Chip-Erase Command Sequence Write data: AAH Address: 5555H
Write data: 55H Address: 2AAAH
Write data: 80H Address: 5555H
Write data: AAH Address: 5555H
Write data: 55H Address: 2AAAH
Write data: 10H Address: 5555H
Wait TSCE
Chip-Erase to FFH
1060 F19.0
FIGURE 19: SOFTWARE CHIP-ERASE COMMAND CODES
(c)2005 Silicon Storage Technology, Inc.
S71060-09-000
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512 Kbit Page-Write EEPROM SST29EE512
Data Sheet
PRODUCT ORDERING INFORMATION
SST 29 XX EE 512 XX XXXX - 70 - XXX 4C XX NH - XXX E X Environmental Attribute E1 = non-Pb Package Modifier H = 32 leads or pins Package Type E = TSOP (type 1, die up, 8mm x 20mm) N = PLCC P = PDIP Temperature Range C = Commercial = 0C to +70C I = Industrial = -40C to +85C Minimum Endurance 4 = 10,000 cycles Read Access Speed 70 = 70 ns Device Density 512 = 512 Kbit Function E = Page-Write Voltage E = 4.5-5.5V Product Series 29 = Page-Write Flash
1. Environmental suffix "E" denotes non-Pb solder. SST non-Pb solder devices are "RoHS Compliant".
Valid combinations for SST29EE512 SST29EE512-70-4C-NH SST29EE512-70-4C-NHE SST29EE512-70-4I-NH SST29EE512-70-4I-NHE SST29EE512-70-4C-EH SST29EE512-70-4C-EHE SST29EE512-70-4I-EH SST29EE512-70-4I-EHE SST29EE512-70-4C-PH
Note: Valid combinations are those products in mass production or will be in mass production. Consult your SST sales representative to confirm availability of valid combinations and to determine availability of new combinations. Note: The software Chip-Erase function is not supported by the industrial temperature part. Please contact SST if this function is required in an industrial temperature part.
(c)2005 Silicon Storage Technology, Inc.
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512 Kbit Page-Write EEPROM SST29EE512
Data Sheet
PACKAGING DIAGRAMS
TOP VIEW
Optional Pin #1 Identifier .048 .042 .495 .485 .453 .447
2 1 32
SIDE VIEW
.112 .106 .020 R. MAX. .029 x 30 .023 .040 R. .030
BOTTOM VIEW
.042 .048 .595 .553 .585 .547 .032 .026
.021 .013 .400 .530 BSC .490
.050 BSC .015 Min. .050 BSC .095 .075 .140 .125 .032 .026
Note: 1. Complies with JEDEC publication 95 MS-016 AE dimensions, although some dimensions may be more stringent. 2. All linear dimensions are in inches (max/min). 3. Dimensions do not include mold flash. Maximum allowable mold flash is .008 inches. 4. Coplanarity: 4 mils.
32-plcc-NH-3
32-LEAD PLASTIC LEAD CHIP CARRIER (PLCC) SST PACKAGE CODE: NH
(c)2005 Silicon Storage Technology, Inc.
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512 Kbit Page-Write EEPROM SST29EE512
Data Sheet
1.05 0.95 Pin # 1 Identifier 0.50 BSC
8.10 7.90
0.27 0.17
18.50 18.30 DETAIL 1.20 max. 0.70 0.50 20.20 19.80
0.15 0.05
0- 5 0.70 0.50 Note: 1.Complies with JEDEC publication 95 MO-142 BD dimensions, although some dimensions may be more stringent. 2.All linear dimensions are in millimeters (max/min). 3.Coplanarity: 0.1 mm 4.Maximum allowable mold flash is 0.15 mm at the package ends, and 0.25mm between leads.
1mm 32-tsop-EH-7
32-LEAD THIN SMALL OUTLINE PACKAGE (TSOP) 8MM X 20MM SST PACKAGE CODE: EH
(c)2005 Silicon Storage Technology, Inc.
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512 Kbit Page-Write EEPROM SST29EE512
Data Sheet
32
C L
Pin #1 Identifier
1
.075 .065 Base Plane Seating Plane
1.655 1.645
7 4 PLCS. .200 .170
.625 .600 .550 .530
.050 .015 .100 BSC .150 .120
.012 .008 .600 BSC
0 15
.080 .070
.065 .045
.022 .016
Note: 1. Complies with JEDEC publication 95 MO-015 AP dimensions, although some dimensions may be more stringent. 2. All linear dimensions are in inches (max/min). 3. Dimensions do not include mold flash. Maximum allowable mold flash is .010 inches. 32-pdip-PH-3
32-PIN PLASTIC DUAL IN-LINE PINS (PDIP) SST PACKAGE CODE: PH
(c)2005 Silicon Storage Technology, Inc.
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512 Kbit Page-Write EEPROM SST29EE512
Data Sheet TABLE 11: REVISION HISTORY
Number 06 07 Description Date May 2002 Mar 2003
* * * * * * * * * * *
2002 Data Book WH package is no longer offered Removed the SST29EE512 90 ns Read Access Time Removed the SST29LE512 200 ns Read Access Time Removed the SST29VE512 250 ns Read Access Time Clarified IDD Write to be Program and Erase in Table 6 on page 9 2004 Data Book Added non-Pb MPNs and removed footnote (See page 22) Removed 2.7V and 3V devices and associated MPNs refer to EOL Product Data Sheet S71060(01). Added RoHS compliance information on page 1 and in the "Product Ordering Information" on page 22 Clarified the Solder Temperature Profile under "Absolute Maximum Stress Ratings" on page 8
08 09
Nov 2003 Sep 2005
Silicon Storage Technology, Inc. * 1171 Sonora Court * Sunnyvale, CA 94086 * Telephone 408-735-9110 * Fax 408-735-9036 www.SuperFlash.com or www.sst.com
(c)2005 Silicon Storage Technology, Inc. S71060-09-000 9/05
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